library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX_ANGLE is -- todo el ingles!!!
	port( C1 			 : in std_logic;
		   C2			 :	in std_logic;
		   OUTPUT : out std_logic_vector(28 downto 0)
	);
end MUX_ANGLE;

architecture mux of MUX_ANGLE is
begin
	process(C1,C2)
	    constant deltafip: std_logic_vector(28 downto 0):=std_logic_vector(to_signed(703125,29));
	    constant deltafin: std_logic_vector(28 downto 0):=std_logic_vector(to_signed(-703125,29));
	    variable control: std_logic_vector (1 downto 0); 
	begin
		 control:=C1 & C2;
		 case control is
		     when "01" =>
		         OUTPUT <= deltafip;
		     when "10" =>
		         OUTPUT <= deltafin;
		     when others =>
		         OUTPUT <=(28 downto 0 => '0');
		 end case;
	end process;
end mux;

--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.numeric_std.all;

--entity test_mux is
--end test_mux;

--architecture simul1 of test_mux is
--	component MUX_ANGLE is
--	port( C1 			 : in std_logic;
--		   C2			 :	in std_logic;
--		   OUTPUT : out std_logic_vector(28 downto 0)
--	);
--	end component;

--	signal C1 : std_logic:='0';
--	signal C2 : std_logic:='0';
--	signal output : std_logic_vector (28 downto 0);
	
	
--begin
    
--	mux : MUX_ANGLE port map (C1,C2,output);
--	C1 <= not(C1) after 100 ns;
--   C2 <= not(C2) after 200 ns;
	


--end simul1;